1. Field of the Invention
The present invention relates to a method of formulating a load model for glitch analysis that is used to locate a circuit part where a glitch error occurs (an error under the influence of the adjoining circuit) and a recording medium on which there is recorded the load model formulating method in the form of a computer program.
2. Description of the Prior Art
FIG. 8 depicts a circuit configuration for locating a circuit part where a glitch error occurs. In the case where a first circuit is electrically affected by a second circuit adjacent thereto, a coupling capacitance (Cc) develops between wires of the first and second circuits. (The first circuit is commonly called a victim and the second circuit an aggressor; in some cases a plurality of aggressors are present.) In this instance, upon operation of the second circuit, such a pulse-shaped signal change as depicted in FIG. 9 is caused in the first circuit at a point A even if the latter is out of operation. Such a signal change is commonly referred to as a glitch.
When the amount of glitch exceeds a certain value, the resulting pulse is likely to cause malfunction of the first circuit. Hence, when it is expected that a glitch will occur in excess of a certain value, the circuit needs to be corrected to keep the glitch from going beyond a threshold value, which is preset by a circuit analysis. Accordingly, it is necessary to decide the need for circuit correction by accurately estimating the amount of glitch likely to occur in the given circuit configuration.
FIG. 10 shows a known method that accurately estimates the amount of glitch by analyzing a load model representing each wire part by an n-stage π-type RC (n=2 in this example). This method permits highly accurate estimation of the amount of glitch, but requires a large amount of circuit data and hence consumes much time for analysis. Since the number of signal lines in the circuit is nearly a million, it is impractical to calculate the amount of glitch for every signal line.
Hence, it is customary in the prior art to adopt a method that analyzes approximate values of glitches by the use of a load model, then extracts from the load model a circuit part (net) where a glitch error is likely to occur, and makes an analysis with a detailed load model, such as depicted in FIG. 10, to make a final decision on the necessity for circuit correction. The load model used in the prior art is such a π-type load model as shown in FIG. 11. Let represents the sum total of wiring resistance values of a first circuit be represented by R, which is set as the resistance of the π-type load. Let the sum total of earth capacities be represented by Cs and the sum total of coupling capacitances by Cc. Each capacitance component is divided using an empirically preset coefficient β (where 0<β<1), and is connected in an inverse ratio. A first circuit driver is approximated by a resistor of a resistance value Rs. To the other end of the coupling capacitance Cc is input a waveform distortion that is observed at a terminal T1 of a second circuit driver. Incidentally, the waveform distortion that is observed at the terminal T1 is an amount that is obtained in an ordinary signal propagation delay calculating stage.
Since the conventional load model has such a configuration as described above, the load configuration is simple and always remains the same, and since only the value of each element or the amount of waveform distortion changes, the conventional load model permits fast calculation of the glitch value. However, the glitch value thus calculated seriously differs from the actual glitch value for the reasons given below.
1. Since the dividing ratio β is a value obtained empirically and does not depend on the actual circuit configuration, the division of each capacitance component may sometimes become inappropriate.
2. Since the resistance value R and the capacitance value C are each in the form of sum total and since the dividing ratio is also fixed, the same load model is always formulated and the same analysis result is produced even for circuit configurations that differ only in the coupling position, for example. In practice, however, different coupling positions provide different glitch values.
3. The waveform distortion at the terminal T1, which is used as the input waveform of the coupling capacitance Cc of the second circuit, is the steepest in the wiring of the second circuit; hence, in some cases the glitch value becomes larger than the actual value. Further, the same glitch value is produced regardless of whether signals propagate in the same or different directions in the first and second circuits, but in practice, the glitch value differs according to the direction of signal propagation.
When the calculated glitch value greatly differs from the actual one, it may sometimes remain undetected as an error. As a solution to this problem, it is necessary to employ a method that makes, in a simple calculation stage, an error decision under stricter conditions than in the case of usual error decision and uses a detailed load model to decide whether the error decision is true or not. Moreover, there are cases where the difference between the calculated glitch value and the actual one, which need not be decided as an error, is classified to be an error candidate as a large glitch value through simple analysis; hence, many signal lines are selected as signal lines that need to be subjected to a detailed error analysis. However, it is considered that such signal lines mostly have no problem. Accordingly, the prior art conducts a detailed analysis of an unnecessarily large number of signal lines, and hence it is time-consuming.